Lossless compression algorithm for hierarchical IC layout data

Abstract

An important step in today's Integrated Circuit (IC) manufacturing is optical proximity correction (OPC). While OPC increases the fidelity of pattern transfer to the wafer, it also significantly increases IC layout file size. This has the undesirable side effect of increasing storage, processing, and I.O. times for subsequent steps of mask preparation. To alleviate the growing volume of layout data, a new layout data format, Open Artwork System Interchange Standard (OASIS), was introduced in 2001 by SEMI's Data Path Task Force. Even though OASIS results in a more efficient representation than the previous industry standard format GDSII, there is still room for improvement by applying data compression techniques. In this paper, we propose two such techniques for compressing layout data, including OPC layout, while remaining complaint with existing industry standard formats such as OASIS and GDSII. Such compliance ensures that the resulting compressed files can be viewed, edited, and manipulated by industry standard CAD viewing and editing tools without the need for a decoder. Our approach is to eliminate redundancies in the representation of the geometrical data by finding repeating groups of geometries between multiple cells and within a cell. We refer to the former as inter-cell sub-cell detection (InterSCD) and latter as intra-cell sub-cell detection (IntraSCD). We show both problems to be NP hard, and propose two sets of heuristics to solve them. For OPC layout data, we also propose a fast compression method based on IntraSCD which utilizes the hierarchical information in the pre-OPC layout data. We show that the IntraSCD approach can also be effective in reconstructing hierarchy from flattened layout data. We demonstrate the results of our proposed algorithms on actual IC layouts for 90nm, 130nm, and 180nm feature size circuit designs.