Loss-aware routing algorithm for photonic networks on chip

Abstract

Photonic network on chip was introduced as an efficient communication platform to overcome the existing challenges in traditional networks on chip. Optical networks provide high bandwidth and low power dissipation infrastructure. Insertion loss is one of the important parameters in photonic networks on chip. In this study, we propose a solution in routing algorithm level in order to reduce insertion loss in photonic network on chip, by passing packets through paths with lower number of optical elements. Simulation results reveal that a novel approach in the routing level decreases insertion loss as much as possible, energy consumption and optical power budget. Our proposed routing has 29.05% less insertion loss under all2all traffic pattern for blocking torus topology, and it has about 12.37% less insertion loss for TorusNX topology in comparison with primary dimension-ordered routing. Proposed routing algorithm increases both the network bandwidth and scalability.