Loop unrolling for second order recursive digital filter to achieve high throughput

Abstract

With the quick progression in technology, there is a ton of potential and interest for high speed signal processing particularly to accomplish high throughput required in real-time critical applications. There are various mixture of strategies exist for making strides in the throughput of the Digital system [1]. Parallel processing is one of the strategies which can be given to digital systems for achieving higher throughput simultaneously in the same hardware unit. Main target of this project is to verify parallel processing in second order IIR filter. Three consecutive processing loops are unfolded in the time domain and parallel hardware is implemented [3]. The design can be verified by using Verilog Hardware description Language and the functionality of the filter is verified by the simulations obtained. The corresponding impulse response from the MATLAB verifies the implementation. The critical path is obtained from the timing report of synthesis. The area and power in each case is computed.