Loop scheduling with memory access reduction under register constraints for DSP applications

Abstract

In embedded systems, high-performance DSP needs to be performed not only with high-data throughput but also with low-power consumption. In this paper, we propose an effective scheduling framework, MARLS (Memory Access Reduction Loop Scheduling), to reduce memory accesses for DSP applications with loops. In the framework, we generate register operations to replace redundant load operations, and schedule these operations while allocating available physical registers to their register operands. We implement our technique into the Trimaran compiler and conduct experiments using a set of benchmarks from DSPstone and MiBench on the cycle-accurate VLIW simulator of Trimaran. The experimental results show that our technique significantly reduces the number of memory accesses.