Long-term annealing of a radiation-hardened 1.0 micron bulk CMOS process

Abstract

Data are reported on the degradation of transistor parameters due to a high-dose-rate irradiation (300 rad(Si)/s) followed an anneal cycle. The parametric data were selected to quantify the loss in drive performance as well as leakage due to the parasitic components. Transistors were annealed at 250 degrees C and 100 degrees C. The recovery of the device parametrics for the n-channel transistors did not show a significant rebound problem. The p-channel transistors did show a small recovery, but became stable after approximately 100 h of annealing. The rate of recovery for the n-channel threshold voltage as a function of anneal temperature was modeled. There are two recovery mechanisms that influence the shape of the recovery curve: (1) electron tunneling into the trapped positive charge, which dominates during the first 1000 h and follows a logarithmic relationship with time; and (2) interface state buildup, which becomes the dominant mechanism during the remainder of the anneal cycle and follows a linear relationship with time.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>