Logic synthesis method for pattern matching circuits implementation in FPGA with embedded memories

Abstract

This paper presents a new cost-efficient realization scheme of pattern matching circuits in FPGA structures with embedded memory blocks (EMB). The general idea behind the proposed method is to implement combinational circuits using a net of finite state machines (FSM) instead. The application of functional decomposition method reduces the utilization of resources by implementing FSMs using both EMBs and LUT-based programmable logic blocks available in contemporary FPGAs. Experimental results for the proposed method are also shown. A comparison with another dedicated method yields extremely encouraging results: with a comparable number of EMBs, the number of logic cells has been reduced by 95%.