Abstract
It is shown how to modify a conventional logic editor-simulator to make it suitable for design of rapid single flux quantum (RSFQ) circuits containing thousands of Josephson junctions. The key new component of the simulator is a library of RSFQ cells. This library has been developed based on an original representation of timing constraints in RSFQ of these constraints. The extended tool supports detection and location of logic design errors in an RSFQ circuit, estimation of circuit speed and throughput, and optimization of the general architecture of the circuit and its synchronization scheme. It is shown how the RSFQ editor-simulator has been employed for designing a decimation filter, a component of a digital signal processing chip currently under development at the University of Rochester. >
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