Logic partitioning to pseudo-exhaustive test for BIST design

Abstract

Built-In Self-Test (BIST) has been proposed as a powerful solution to VLSI testing problem and pseudo-exhaustive test is a BIST design methodology that provides effective, 100% fault coverage for all testable stuck-at faults. A circuit partitioning method is presented to partition the digital combinational portions of a circuit into different structural subcircuits so that each subcircuit can be pseudo-exhaustively tested. Furthermore, a tight lower bound on the number of interconnections between distinct subcircuits is derived. These interconnections are required for self-testing each subcircuit when the circuit is partitioned into a specified number of groups of specified sizes. We demonstrate the effectiveness of partitioning method by illustrations of applying the method to circuit examples, benchmark circuits and practical VLSI designs.