Logic Locking in Single Flux Quantum Circuits

Abstract

The hardware security of RSFQ circuits has become an issue of growing importance for prospective exascale computing systems. Hardware security in RSFQ circuits is particularly relevant to large scale data centers operating with sensitive information. The number of fabrication facilities for superconductive niobium-based technology is limited, and the supply chain for distributing fabricated circuits can be compromised. Logic locking is widely used in modern CMOS circuits to enhance security by masking the functionality of the circuit using a secret key. If an attacker possesses a physical circuit secured by logic locking, the attacker would be unable to determine the intended function. In this paper, a novel methodology for logic locking is proposed for SFQ circuits. Mutual inductances are used to apply additional currents to some or all of the logic gates. These currents behave as keys to access the functionality of the SFQ logic elements. In the proposed technique, only after an additional correct current is applied to all of the locked gates will the circuit produce the proper output. By using inductors with a positive and negative mutual inductance connected to the internal inductances of the gates, the range of current required to unlock a secured circuit is greatly narrowed. In this work, the operation of this proposed logic locking technique is demonstrated using modified SFQ OR gates to enable security while maintaining proper functionality. Less than 4% area overhead is achieved.