Abstract
Logic CMOS device scaling trend is described along the International Technology Roadmap for Semiconductors (ITRS) 2007 edition. For transistor performance improvement, geometrical scaling of gate length still plays an important role. At the same time, equivalent scaling such as metal gate and mobility enhancement is also indispensable. In order to break through the improvement limitation of planar bulk structure, new transistor structure such as FinFET will be introduced from 2010 or 2011 time frame. In long term, alternative materials and structures will be required to realize extremely high ballistic transport.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
