Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality

M Beck,M Kaibel,R Press,Xijiang Lin Xijiang Lin,O Barondeau,F Poehl

doi:10.1109/date.2005.199

Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality

M Beck, M Kaibel + Show 4 more

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https://doi.org/10.1109/date.2005.199

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Publication Date: Oct 24, 2007

Citations: 61

Affiliation: Infineon Technologies (Germany), Mentor Technologies

#Delay Test Quality #Clock Generation + Show 8 more

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Abstract

This paper addresses delay test for SOC devices with high frequency clock domains. A logic design for on-chip high-speed clock generation, implemented to avoid expensive test equipment, is described in detail. Techniques for on-chip clock generation, meant to reduce test vector count and to increase test quality, are discussed. ATPG results for the proposed techniques are given.

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