Logic Circuit Based Test Derivation for Microcontrollers

Abstract

In this paper, an approach to test synthesis based on a logic circuit model for microcontroller based physical systems is described. The formal model of the logic circuit is used to describe the behavior of discrete systems with a finite number of transitions. A model of a higher level of abstraction is a Finite State Machine (FSM) and its modifications, for example, a timed Finite State Machine (TFSM). These formal models are used to synthesize complete test suites for discrete systems with respect to a given fault model. A fault model based on three popular faults in logic circuits is often used to derive complete test suites for logic circuits. According to a previous experimental result, such complete test suites can detect a large number of output faults in the corresponding FSM. The advantage of the logic circuit model is scalability, which allows building tests with sufficiently high fault coverage, in the case when the FSM of the system under test has a large number of states and the test synthesis process becomes difficult. The paper describes the application of this approach to the microcontroller based system of a switching generator, whose behavior is described by a TFSM. The number of states of corresponding FSM abstraction increases significantly so an FSM based test derivation process becomes more complex.