Localization of burn mark under an abnormal topography on MOSFET chip surface using liquid crystal and emission microscopy tools

Abstract

This article focuses on the localization of burn mark in MOSFET and the scanning electron microscope (SEM) inspection on the defect location. When a suspect abnormal topography is shown on the die surface, further methods to pin-point the defect location is necessary. Fault localization analysis becomes important because an abnormal spot on the chip surface may and may not have a defect underneath it. The chip surface topography can change due to the catastrophic damage occurred at layers under the chip surface, but it could also be due to inconsistency during metal deposition in the wafer fabrication process. Two localization techniques, liquid crystal thermography and emission microscopy, were performed to confirm that the abnormal topography spot is the actual defect location. The tiny burn mark was surfaced by performing a surface decoration at the defect location using hot hydrochloric acid. SEM imaging, which has the high magnification and three-dimensional capabilities, was used to capture the images of the burn mark.