Abstract
In most processors, caches account for the largest fraction of onchip transistors, thus being a primary candidate for tackling the leakage problem. Existing architectural solutions usually rely on customized cache structures, which are needed to implement some kind of power management policy. Memory arrays, however, are carefully developed and finely tuned by foundries, and their internal structure is typically non accessible to system designers. In this work, we focus on the reduction of leakage energy in caches, without interfering with its internal design. We proposed a truly architectural solution that is based on cache sub-banking and on the detection and mapping of the application localities, detected from a profiling of the cache access patterns. By customizing the mapping between the application address space and the cache, we can expose as much address space idleness as possible, thus resulting in shutdown potential which allows significant leakage saving. Results show leakage energy reduction of up to 48% (about 30% on average), with marginal impact on miss rate or execution time.
Published Version
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