Local charge accumulation and trapping in grain boundaries of pentacene thin film transistors

Abstract

We present a comprehensive Kelvin probe force microscopy study of grain boundaries in pentacene transistors with different film thicknesses in combination with current–voltage measurements and 3D electrostatics simulations. It is found that in pentacene films thinner than approximately 30 nm, holes are accumulated in the grain boundaries due to negative trapped charge at the SiO 2–pentacene interface. On the other hand, in thicker films we observe hole depletion near the boundaries mainly due to positive charge trapping in the grain boundaries. The results are discussed in view of their effect on pentacene thin film transistors performance.