Local capacitance-voltage profiling and high voltage stress effect study of SiO2/SiC structures by time-resolved scanning nonlinear dielectric microscopy

Abstract

We investigate SiO2/SiC structures by a nanoscale capacitance-voltage (CV) profiling method based on time-resolved scanning nonlinear dielectric microscopy (tr-SNDM). Owing to the high sensitivity to the variation in the tip-sample capacitance, wide bandwidth of the measurement, and high flexibility of offline processing, tr-SNDM permits the more accurate acquisition of the microscopic CV characteristics localized below the scanning tip. We demonstrate that tr-SNDM based local CV profiling is able to distinguish the different features of untreated and nitrided SiO2/SiC structures and image intrinsic spatial non-uniformity of the interfaces. We also investigate the nanoscale impacts of high voltage stress on the SiO2/SiC structures. By inspecting the local CV characteristics under high voltage stress, we suggest that the interface defect density locally increases during the stress application.