Abstract

The use of $LLC$ resonant converters has gained popularity in multiple applications that require high conversion efficiency and galvanic isolation. In particular, many applications like portable devices, flat TVs, and electric vehicle battery chargers require demanding slim-profile packaging and enforce the use of planar transformers (PTs) with low-height, low leakage inductance, excellent thermal characteristics, and manufacturing simplicity. The main challenge in successfully designing $LLC$ converters with PT resides in controlling high-parasitic capacitances produced by large overlapping layers in PT windings. When the parasitic capacitances are not controlled, they severely impair the converters’ performance and regulation, and limit the application of PTs in high-frequency $LLC$ converters. This paper characterizes the PT capacitance issue in detail and proposes mitigation strategies to improve the performance of $LLC$ converters with PTs. A systematic analysis is performed, and six PT winding layouts are introduced and benchmarked with a traditional design. As a result of the investigation, an optimized structure is obtained, which minimizes both the interwinding capacitance and ac resistance, while improving the regulation performance of $LLC$ converters. Experimental measurements are presented and show a significant reduction of parasitic capacitance by up to 21.2 intra- and 16.6 interwinding capacitances, without compromising resistance. This substantial capacitance reduction has a tangible effect on the regulation performance of $LLC$ resonant converters. Experimental results of the proposed PT structure in a 1.2 kW $LLC$ resonant converter show a reduction in common-mode noise, extended output voltage regulation, and improved overall efficiency of the converter.

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