Lithography-Free Nanostructure Fabrication Techniques Utilizing Thin-Film Edges

Abstract

Fabricating nanoscale patterns with sub-10 nm feature size has been an important research target for potential applications in next-generation memories, microprocessors, logic circuits and other novel functional devices. Typically, according to the International Technology Roadmap for Semiconductor (ITRS) from 2009, an 8.9 nm node device is targeted for the year 2024. To achieve this milestone, liquid immersion lithography and extreme ultraviolet (EUV) lithography can be expected to be among the most commonly used techniques for the fabrication of nanopatterns. With liquid immersion lithography using a wavelength of 193 nm and a high numerical aperture (NA), it has been demonstrated that 32 nm features can be patterned (Finders et al., 2008; Sewell et al., 2009). EUV lithography using a short wavelength of 13.5 nm and 0.3-NA exposure tool has also enabled the printing of 22 nm half-pitch lines (Naulleau et al., 2009). On the other hand, attractive patterning techniques, such as a superlattice nanowire pattern transfer (SNAP) method (Melosh et al., 2003; Green et al., 2007), a mold-to-mold cross imprint (MTMCI) process (Kwon et al., 2005) and a surface sol-gel process combined with photolithography (Fujikawa et al., 2006), are currently proposed and pursued actively. The SNAP method, which is based on translating thin film growth thickness control into planar wire arrays, has enabled the production of molecular memories consisting of 16 nm wide titanium/silicon nanowires. The MTMCI process using silicon nanowires formed by spacer lithography, in which nanoscale line features are defined by the residual part of a conformal film on the edges of a support structure with the linewidth controlled by the film thickness, has been used to produce a large array of 30 nm wide silicon nanopillars. With the surface sol-gel process combined with photolithography, where the linewidth is determined by the thickness of coating silica layer on the resist pattern, the size reduction and the large area of sub-20 nm silica walls have been achieved. Recently, we have proposed a double nano-baumkuchen (DNB) structure, in which two thin slices of alternating metal/insulator nano-baumkuchen are attached so that the metal/insulator stripes cross each other, as part of a lithography-free nanostructure fabrication technology (Ishibashi, 2003 & 2004; Kaiju et al., 2008; Kondo et al., 2008). The schematic illustration of the fabrication procedure is shown in Fig. 1. First, the metal/insulator spiral heterostructure is fabricated using a vacuum evaporator including a film-rolled-up system. Then, two thin slices of the metal/insulator nano-baumkuchen