Linearization of subthreshold low-noise amplifiers

Abstract

This paper presents a subthreshold cascode low-noise amplifier (LNA) with inductive source degeneration and third-order linearity enhancement. The LNA architecture includes an inductor and a capacitor at the gate of the cascode transistor for partial cancellation of third-order distortion components. This design method enables third-order intermodulation intercept point (IIP3) and 1dB compression point (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> ) improvements of 4.8-11.2 dB and 7.1-11.6 dB respectively (depending on the process corner case) compared to a commensurate LNA without the linearization method. A 2.4 GHz LNA was designed and simulated using 0.13 μm CMOS technology. In the typical corner case, the linearized LNA achieves -2.0 dBm IIP3, -13.5 dBm P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> , 18.2 dB power gain, and 4.54 dB noise figure with a power consumption of 0.24 mW.