Linearization of stacked‐fet RF CMOS power amplifier using diode‐integrated bias circuit

Abstract

AbstractIn this article, the linearization circuit of stacked‐FET RF CMOS power amplifier (PA) is presented. The proposed diode‐integrated bias circuit provides the increasing DC gate bias current which allows the bottom FET in the tripled‐stacked FET to saturate at a higher power compared to the conventional bias circuit. The simulation shows that the proposed bias circuit can increase a 1‐dB gain compression point of the stacked‐FET PA with a higher efficiency. It is demonstrated from the measurement of the triple‐stacked CMOS PAs with W‐CDMA input signal that the proposed diode‐integrated bias circuit can reduce the spectrum regrowth and increase the average efficiency. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:1011–1014, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27472