Linear timing analysis of SOC synchronous circuits with level-sensitive latches

Abstract

This paper describes a linear programming (LP) formulation applicable to the timing analysis of large scale SOC synchronous circuits with level-sensitive latches. The proposed formulation uses a variation of the big M method (W. L. Winston, Operations Research Application and Algorithms, PWS-Kent Publ. Co., 2nd ed., 1991) to modify the nonlinear constraints in the problem formulation into solvable linear constraints. By making maximum use of cycle stealing (I. Lin et al, Proc. 29th ACM/IEEE Design Automation Conf., pp. 393-398, 1992), operation at a higher clock frequency (reduced clock period) is possible. The industrial LP solver CPLEX is used on the ISCAS'89 benchmark circuits, demonstrating significant improvements in clock period.