Abstract

A novel hardware realisation for linear phase decimation and interpolation FIR filters, exploiting the symmetry of the coefficients to reduce the number of multipliers, will be described. Combining the multiplications, leads to contra-dataflow or folded filter structures in which simple pipelining is limited, because of the opposite directions of the data flows. It will be shown that these structures can be transformed into new filter structures, which allow conventional pipelining to relax the timing demands for high-speed applications.

Full Text
Paper version not known

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.