Linear CMOS image sensor with time-delay integration and interlaced super-resolution pixel

Abstract

This paper presents a high frame rate linear scan CMOS image sensor (CIS) with time-delay integration (TDI) technique and interlaced super-resolution (ISR) pixel to increase signal-to-noise ratio (SNR) and horizontal resolution. An adjacent pixel signal transfer (APST) methodology is adopted for efficient wire routing and reducing pixel complexity. 4T-APS is applied in pixel to achieve the snapshot function. A 128×8×2 interlaced super-resolution pixel array with a pitch of 6×6 um <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , a fill factor of 26.99%, and 3.3V operation has been designed and fabricated in 0.18-um TSMC 1P6M CIS technology. Two 128×8 linear array are placed in an interlaced form with a half-pixel-pitch shift to achieve the super-resolution output. The measurement results of proposed linear scan sensor with 8 TDI stages and ISR technique demonstrate a SNR improvement of 10.3 dB, double horizontal resolution, and a power dissipation of 4.114uW per column at 1.6kfps.