Limits of low noise performance of detector readout front ends in CMOS technology

Abstract

The limits of the noise performance of detector readout front ends in CMOS technology have been studied. A theoretical minimal number of equivalent noise charge (ENC) that can be achieved by a CMOS technology is derived, taking both thermal noise and 1/f noise into account. Design criteria and techniques of CMOS readout front ends are presented so as to fully exploit the maximal capability of a CMOS technology. The optimal input transistor dimensions and bias conditions of charge sensitive amplifiers (CSA) are analytically determined. For readout front ends using semi-Gaussian pulse shapers, the optimal number of integrators and the optimal peaking time are determined from the point of view of achieving the best detector resolution. In order to verify the theoretical analyses, a charge sensitive amplifier and a fourth-order semi-Gaussian pulse shaper with 1- mu s peaking time have been designed in a standard 3- mu m CMOS technology. Calculations and computer simulations show that by optimal design of input CSA and semi-Gaussian pulse shaper, a detector resolution as low as 600 equivalent noise electrons can be obtained for a 40-pF detector capacitance. >