Limited Address Range Architecture for Reducing Code Size in Embedded Processors

Abstract

In embedded systems a processor core must be designed with low power consumption, low cost and small silicon area in mind since program code often resides in on-chip ROM. To obtain small code size, not only the amount of instruction-level parallelism can be restricted by instruction sets, but also the encoding cost can be reduced by restricting the access to register files. However, communication among register files has to be supported by hardware, e.g. buses and wires, and compilers. In this paper, we propose a new type of architecture by limiting the encoding range to a subset of registers in a register file on the one hand, and keeping the overlap among different ranges on the other hand in order to support communication between all the functional units. We also propose the annotated conflict graph approach for modeling the range constraints in this architecture, which can be applied in combination with any scheduler. However, to overcome the phase coupling between address range assignment and scheduling in code generation, in this paper the address range constraints are transformed and integrated with the existing timing, resource and register file constraints. Constraint analysis techniques [9] are adapted to prune the search spaces based on those constraints. Results show that we can reduce code size up to 24.58% by applying our technique.