Limitations of the High–Low $C$ –$V$ Technique for MOS Interfaces With Large Time Constant Dispersion

Ashish Verma Penumatcha,James A Cooper,Steven Swandono

doi:10.1109/ted.2013.2237777

Limitations of the High–Low $C$ –$V$ Technique for MOS Interfaces With Large Time Constant Dispersion

Ashish Verma Penumatcha, James A Cooper + Show 1 more

https://doi.org/10.1109/ted.2013.2237777

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Journal: IEEE Transactions on Electron Devices	Publication Date: Mar 1, 2013
Citations: 56

Affiliation: Purdue University West Lafayette

#High-low Technique #MOS Samples + Show 8 more

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Abstract

We discuss the limitations of the high-low CV technique in evaluating the interface trap density (DIT) in MOS samples with a large time constant dispersion, as occurs in silicon carbide (SiC). We show that the high-low technique can seriously underestimate DIT for samples with large time constant dispersion, even if elevated temperatures are used to extend the range of validity.

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