Abstract
A single event causing a double-node upset is likely to occur in nanometric complementary metal-oxide-semiconductor (CMOS). Contemporary hardened latch designs are insufficient in meeting high reliability, low power consumption, and low delay. This paper presents a novel soft error hardened latch, known as a loop interlocked hardened latch (LIHL). This latch consists of four modified cross-coupled elements, based on dual interlocked storage cell (DICE) latch. The use of these elements hardens the proposed LIHL to soft errors. The simulation results showed that the LIHL has single-event double upset (SEDU) self-recoverability and single-event transient (SET) pulse filterability. This latch also reduces power dissipation and propagation delay, compared to other SEDU or SET-tolerant latches.
Highlights
A soft error is generated when a particle strikes a sensitive node within a memory element—such as a latch or flip-flop—and changes its logic values [1,2,3]
Aiming for soft errors tolerance, this paper proposed a novel loop interlocked hardened latch (LIHL)
Compared with dual interlocked storage cell (DICE), which is only capable of single-event upset (SEU) tolerance, LIHL has the capacity for SEU, single-event double-upset (SEDU), and single-event transient (SET) tolerance
Summary
A soft error is generated when a particle strikes a sensitive node within a memory element—such as a latch or flip-flop—and changes its logic values [1,2,3]. The proposed design used four improved cross-coupled elements based on DICE This design is capable of self-recovering from SEU, tolerating SEDU, and filtering SET pulses. This schematic uses double modular redundancy technology to replicate the non-radiation hardened circuit and connect it to a multi-input C-element as a voter This latch uses multi-input C-elements to form a feedback loop to store data, and uses a transmission gate to connect input and output to build a fast path to reduce delay. This latch is mainly constructed from a storage module in the left part and a clock-gating based error-interceptive four-input C-element in the right part This structure can tolerate SEDU but cannot self-recover and is sensitive to the high-impedance state. X1, X2, X3, and X0 were similar to the state of upset to recovery
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