Abstract

User and device biometrics are proven to be a reliable source for authentication, especially for the Internet-of-Things (IoT) applications. One of the methods to employ biometric data in authentication are fuzzy extractors (FE) that can extract cryptographically secure and reproducible keys from noisy biometric sources with some entropy loss. It has been shown that one can reliably build an FE based on the learning parity with noise (LPN) problem with higher error-tolerance than previous FE schemes. However, the only available LPN-based FE implementation suffers from extreme resource demands that are not practical for IoT devices. This article proposes a lightweight hardware/software (HW/SW) co-design for implementing LPN-based FE. We provide different optimizations on architecture to decrease the resource requirements of the scheme. The proposed architecture is resistant against simple side-channel analysis and improves area and area-time product (AT) by more than 89% and 83%, respectively, compared to previous work. Our experimental results indicate that the proposed architecture can be implemented on off-the-shelf resource-constrained SoC-FPGA boards from different vendors such as Xilinx, Digilent, and Trenz. Moreover, we provide the first implementation results of LPN-based FE on an application-specific integrated circuit (ASIC) platform using HW/SW co-design.

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