Lightweight and High-Performance Data Protection for Edge Network Security

Abstract

To strengthen the security of edge network data and reduce network latency, in this paper, we combine an advanced reduced instruction set computing machine (ARM) and a field programmable gate array (FPGA) to propose a lightweight ARM-FPGA computing architecture for edge network data security protection and acceleration. Firstly, the access control lists are set through FPGA to authorize and filter illegal data, thereby reducing the transmission and processing of invalid data on the network. Secondly, based on the principles of dynamization, diversification, and randomization, the initial random key is generated using a pseudo-random number generator and a scrambling factor, and the hash of the data packet value updates the key to ensure “one frame, one key.” Then, an ARM microprocessor is used to monitor the working status of the system in real-time. If an abnormality is found, different disturbance factors are activated using key management to change the system running status and restore the stability of the system. Finally, pipeline technology and critical path optimization on FPGA are used to parallelize the underlying encryption algorithm and data compression algorithm to achieve high-speed memory communication and meet the performance requirements of different networks. The experimental and analysis results show that the computing architecture designed in this paper has high network encryption performance and can effectively prevent data leakage. In addition, the effectiveness of the architecture in terms of network delay and network load is verified.