Lifetime control in silicon devices by voids induced by He ion implantation

Abstract

A method to control carrier lifetime in silicon locally and efficiently is presented. Voids, formed by high dose He implants, have been characterized by transmission electron microscopy demonstrating they are well localized in depth within layers thinner than 100 nm while their lateral extent is limited only by the masking capability during He implantation. Deep level transient spectroscopy measurements, performed on diodes containing different void densities, revealed the presence of two well defined trap levels, independent of void characteristics, at Ev+0.53 for holes and Ec−0.55 for electrons. These characteristics make them ideal for lifetime control in reducing parasitic transistor gain. Gummel plots on transistors have shown that when voids are formed the gain decreases from 1 to 10−3. The other transistor characteristics are only slightly influenced by the presence of voids.