LI-BIST: a low-cost self-test scheme for SoC logic cores and interconnects

Abstract

For deep sub-micron system-on-chips (SoC), interconnects are critical determinants of performance, reliability and power Buses and long interconnects being susceptible to crosstalk noise, may lead to functional and timing failures. Existing at-speed interconnect crosstalk test methods are based on either (i) inserting dedicated interconnect selftest structures (leading to significant area overhead), or (ii) using existing logic BIST structures (e.g., LFSRs), which often result in poor defect coverage. Additionally, it has been shown that the power consumed during testing can potentially become a significant concerti. In this paper we present Logic-Interconnect BIST (LI-BIST), a comprehensive self-test solution for both the logic of the cores and the SoC interconnects. LI-BIST reuses existing LFSR structures but generates high-quality tests for interconnect crosstalk defects, while minimizing area overhead and interconnect power consumption. On applying LI-BIST to a DSP chip, we achieved crosstalk defect coverage of 99.7% for the interconnects and single stuck-at-fault coverage of 91.36% for the logic cores, while incurring an area overhead of only 4% over conventional logic BIST.