LHC-ATLAS Phase-1 upgrade: firmware validation for real time digital processing for new trigger readout system of the Liquid Argon calorimeter

R Oishi

doi:10.1088/1748-0221/15/05/c05013

Abstract

The third run (Run 3) of the ATLAS experiment at CERN's Large Hadron Collider will begin in 2021 in a high luminosity and high energy environment. In this circumstance, an effective trigger system is required. ATLAS uses a two-stage trigger system. The first stage trigger system (Level 1 trigger) is based on hardware, and the second stage is a software-based high-level trigger on a PC farm. With this system, an overall trigger rate is required to be suppressed to 1 kHz or less from a bunch-crossing rate of 40 MHz. In the liquid argon calorimeter level 1 trigger system, new trigger readouts with a factor of ten higher granularity compared to the Run 2 trigger readout, are introduced to suppress backgrounds. By measuring shower shape with the higher granularity, the electron and photon trigger rate can be suppressed sufficiently. To process all data from the supercells, new readout boards are prepared. One of the boards, dubbed LATOME, converts ADC data to transverse energy with fixed latency and sends three types of energies to the Level 1 trigger system. The trigger system uses computed energies with LATOME firmware, and therefore the development and validation of the LATOME firmware is important for the ATLAS data acquisition system. One of the LATOME firmware module, User Code, calculates the transverse energy for all supercells. To ensure all User Code blocks are functional, firmware validation is required. Simulation based firmware verifications and validations with the LATOME are presented with the firmware design.

Highlights

LHC-ATLAS Phase-1 upgrade: Firmware validation for real time digital processing for new trigger readout system of the Liquid Argon calorimeter
Each LAr digital processing board (LDPB) is composed of one carrier board and four LATOME cards embedded with Arria 10 GX FPGA
All of the User Code blocks are driven with 240 MHz and every filtering process must be executed with exactly 27 clock ticks (=112.5 ns). 22 clock ticks are used for data from multiple ADCs and the coefficients and reset of the User Code latency are used to extract the timing of energy depositions

Summary

LATOME firmware

Signals from the LAr calorimeter are digitized with a sampling rate of 40 MHz by the new LAr Trigger Digitizer Board (LTDB), installed in the front-end crate. The digitized data is transmitted via 70-100 m long optical fibers to LAr digital processing board (LDPB) installed in the back-end electronics. Each LATOME receives ADC data from the LTDB with 40 fibers at 204.8 Gbps (5.12 Gbps/fiber) and transmits three types of energies with 40 fibers at 448 Gbps (11.2 Gbps/fiber) to the stage of the level 1 trigger system. LATOME firmware has an IP bus controller and a monitoring module. The IP bus changes LATOME firmware configurations and implements some simple monitoring systems. The monitoring module extracts processed data over a XAUI (10 Giga ethernet) card and sends it to a dedicated PC through the carrier board and ATCA networks. Module Input stage Configurable remap User Code Output summing IP bus controller Monitoring

User Code

Simulation verification

Onboard validation

Findings

Conclusion