LFSR based versatile divider architectures for BCH and RS error correction encoders

Abstract

Error correction codes play a major role in real world data communication systems. This paper proposes linear feedback shift register (LFSR) based flexible and vector serial/parallel dividers for Bose–Chaudhuri–Hocquenghem (BCH) and Reed Solomon (RS) error correction encoders (ECEs). These can be used in variable length error correction codecs. Also, this paper elaborates the versatile hardware implementations of Turbo product encoders using the proposed flexible/vector serial dividers based BCH/RS encoders. The proposed flexible architectures are used to perform the division operation with variable length generator polynomials in BCH and RS based ECEs. In these flexible designs, the same hardware circuit is used to achieve the versatility without much compromise in throughput by allowing the trade-offs in area and power-delay-product (PDP). The proposed vector architectures are used to perform multiple division operations in parallel to improve the throughput with the trade-offs in area and PDP. The proposed and existing designs are implemented using 45 nm CMOS technology. The synthesis results show that the proposed vector designs achieve significant improvement in throughput over the existing designs. For example, the LFSR based proposed vector serial dividers achieve 47.1% and 83.3% of improvement in throughput as compared with the conventional designs for BCH encoder with generator polynomial length 65 and RS encoder with generator polynomial length 17 respectively.