Leveraging Scratchpad Memory in a Hierarchical Architecture for Multicore

Abstract

This paper proposes a novel architecture for multi-core processors, tailored for high-performance parallel computing. The architecture is founded on the innovative notion that complex problems can be decomposed into three relatively independent sub-problems: data processing, data management, and data communication. It features a grid of small, programmable processing units intricately connected to their three neighbouring units, forming a physically scalable and fractal environment. With flexibility, modularity, and scalability as focal points, this architecture aims to address the anticipated real-time signal processing demands in future telecommunication and multimedia systems. One notable aspect of the proposed architecture is its direct support for object-oriented features at the hardware level. Adopting a hybrid approach with Scratchpad Memory (SPM) combined with Cache in the on-chip memory hierarchy enhances performance and adaptability for sophisticated multi-core applications. The study highlights SPM management and introduces a dynamic data management framework. Unlike traditional SPM allocation methods relying on compiler or profiling knowledge, the proposed approach leverages random sampling and probability theory to predict hot-access data during runtime. This dynamic memory access pattern guides SPM allocation, ensuring optimal utilization of SPM's advantages in access speed and energy consumption, complemented by hardware support from DataUnit. This paper presents a paradigm shift in multi-core processor architecture, offering advanced features to meet the evolving requirements of parallel computing, making it well-suited for future telecommunication and multimedia systems. This paper introduces a revolutionary multicore processor architecture designed for high-performance parallel computing. The foundation of the proposed architecture lies in the innovative concept that complex problems can be decomposed into three relatively independent sub-problems: data processing, data management, and data communication. The architecture features a grid of small, programmable processing units, each intricately connected to its three neighboring units, forming a physically scalable and fractal environment. With a focus on flexibility, modularity, and scalability, this architecture addresses the real-time signal processing demands anticipated in future telecommunication and multimedia systems. One distinctive aspect of the proposed architecture is its direct support for object-oriented features at the hardware level. The on-chip memory hierarchy adopts a hybrid approach with Scratchpad Memory (SPM) combined with Cache, enhancing performance and adaptability for sophisticated multi-core applications. The study emphasizes SPM management and introduces a dynamic data management framework. In contrast to traditional SPM allocation methods relying on compiler or profiling knowledge, the proposed approach leverages random sampling and probability theory to predict hot-access data during runtime. This dynamic memory access pattern guides SPM allocation, ensuring optimal utilization of SPM's advantages in access speed and energy consumption, complemented by hardware support from DataUnit. This paper presents a paradigm shift in multicore processor architecture, offering advanced features to meet the evolving requirements of parallel computing, making it well-suited for future telecommunication and multimedia systems