Level-1 silicon vertex detector trigger at Belle

H Kurashiro,S Okuno,K Ueno,T Tsuboyama,J Dalseno,Y Yamashita,T Lesiak,Z Natkaniec,T Higuchi,Y Watanabe,Y Mikami,Y Asano,P Kapusta,J Haba,Y Ushiroda,M Yamauchi,A Kibayashi,S Fratina,S Vahsen,B Harrop,D Heffernan,H Tajima,S Korpar,H Steininger,K Trabelsi,Y Igarashi,S Chidzik,S Nozaki,S Iwaida,A Chouvikov,W Ostrowicz,M Pernicka,K Sumisawa,Y Onuki,T Hara,M Watanabe,T Kawasaki,R Ohkubo,F Ohno,H Miyake,T Nakadaira,Hiroyuki Aihara ,K Hara ,J Schümann ,G.n Taylor ,O Tajima ,S Schmid ,H Ikeda ,Timothy D Browder ,C.c Wang ,A Kusaka ,A M Bakich ,M Friedl ,H Fujii ,H Ishino ,Keníchi Takahashi ,Y Yasu ,Akinori Igarashi ,K.f Chen ,Richard M Dowd ,M Hazumi ,N Sato ,N Tamura ,L S Peak ,Hiroshi Matsumoto ,S T Koike ,F Takasaki ,R Fernholz ,Shunsuke Ono ,K Kasami ,T Aso ,Y Fujiyama ,Y Velikzhanin ,Darja Zontar ,M.-C Chang ,D Marlow ,Takashi Kameshima ,S Stanič ,P Križan ,Jun‐Ichi Suzuki ,H Yamamoto ,M Rosen ,M Tanaka ,G Varner ,M.z Wang ,R Stamen ,Y Chào ,Tadashi Shibata ,T Haruyama ,J Kaneko ,R X Yang ,M Różańska ,Kohei Hayashi ,K Uchida ,M Barbero ,Hiroshi Ozaki ,K E Varvell ,G R Moloney ,T Ziegler

doi:10.1109/nssmic.2004.1462572

Level-1 silicon vertex detector trigger at Belle

H Kurashiro, S Okuno + Show 97 more

https://doi.org/10.1109/nssmic.2004.1462572

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Publication Date: Oct 16, 2004

Affiliation: Tokyo Institute of Technology, Kanagawa University, National Taiwan University, University of Melbourne, Polish Academy of Sciences, Tohoku University, Lawrence Berkeley National Laboratory, Princeton University, Osaka University, The University of Tokyo, Niigata University, University of Sydney

#Silicon Vertex Detector #Central Drift Chamber + Show 8 more

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Abstract

We present a newly developed fast trigger system that uses the silicon vertex detector (SVD) for the Belle experiment at the KEKB energy-asymmetric e/sup +/e/sup -/ collider. It is designed to issue the trigger with a latency of 1.85 /spl mu/s for the Belle central trigger system (GDL). The primary purpose of the SVD trigger is to reduce beam-induced background events by requiring tracks that come from the interaction point. The system receives trigger signals from VA1TA front-end integrated circuits, which read out signals on the silicon-strips. SVD tracks are constructed with them in combination with the trigger information of the central drift chamber (CDC), which is located outside the SVD. Performance of the SVD trigger is evaluated with collision data.

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