Least leakage vector assisted technology mapping for total power optimization

Abstract

As the feature size continues to shrink and the threshold voltage keeps on reducing, leakage power becomes a significant component of the total power consumption. The cost function used in the conventional logic synthesis tools was over simplified in modelling the total power consumption of the logic network. On the other hand, recent works on reducing leakage power mainly focused on an already synthesized network. We propose a complete model of the total power consumption of the logic network which includes the leakage power and also takes into account the operating duty cycle of the applications. In addition, we propose a least leakage vector (LLV) assisted technology mapping to optimize the total power of the final mapped network. The LLV used during technology mapping phase is obtained from the technology decomposed network. Experimental results show that an average of 20% reduction in total power consumption is obtained comparing with the conventional low power technology mapping algorithm.