Leaky Integrate and Fire Neuron by Charge-Discharge Dynamics in Floating-Body MOSFET

Sangya Dutta,Aditya Shukla,Udayan Ganguly,Nihar R Mohapatra,Vinay Kumar

doi:10.1038/s41598-017-07418-y

Sangya Dutta, Aditya Shukla + Show 3 more

Open Access

https://doi.org/10.1038/s41598-017-07418-y

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Abstract

Neuro-biology inspired Spiking Neural Network (SNN) enables efficient learning and recognition tasks. To achieve a large scale network akin to biology, a power and area efficient electronic neuron is essential. Earlier, we had demonstrated an LIF neuron by a novel 4-terminal impact ionization based n+/p/n+ with an extended gate (gated-INPN) device by physics simulation. Excellent improvement in area and power compared to conventional analog circuit implementations was observed. In this paper, we propose and experimentally demonstrate a compact conventional 3-terminal partially depleted (PD) SOI- MOSFET (100 nm gate length) to replace the 4-terminal gated-INPN device. Impact ionization (II) induced floating body effect in SOI-MOSFET is used to capture LIF neuron behavior to demonstrate spiking frequency dependence on input. MHz operation enables attractive hardware acceleration compared to biology. Overall, conventional PD-SOI-CMOS technology enables very-large-scale-integration (VLSI) which is essential for biology scale (~1011 neuron based) large neural networks.

Highlights

The high neuronal density (1011 neurons in the human brain compared to 109 transistors/chip) and connectivity (104 neurons connected to each neuron compared to a typical fan out of 8 in CMOS) imposes two major constraints
We propose to replace the 4-terminal, novel gated ionization based n+/p/n+ diode (I-NPN) device with a conventional 3-terminal, highly manufacturable PD-SOI MOSFET
Intrinsic carrier dynamics of the device produces “Leak Integrate and Fire” functionality. This experimentally validated approach is noted for significant area and power efficiency compared to analog circuit implementation (Supplementary Information 1)

Summary

Background

Pre-synaptic neuronal driver D1 and D2 provide the input voltage spikes (where ith spike occurs at time t = ti). These input spikes are converted to a gently varying current signal proportional to the synaptic weight (wj). The current from synapses (w1and w2) is summed into the input of LIF neuron N3 by the network. The LIF neuron (described in detail ) integrates the input current across a capacitor, which raises its potential. Every time N3 reaches threshold, a driver neuron D3 produces a spike. The detail of this architecture is discussed in ref

10. Among various neuronal

Conclusion

Method