Abstract
AbstractIn very deep submicron technologies (< 0.13 μm) the leakage power consumption becomes an important contribution to total power consumption. Consequently a new low-power design methodology will be required at circuit, architectural and system levels. This paper focuses on architecture comparison and aims at selecting the one with the minimum total power consumption by simultaneously optimizing static and dynamic power dissipation. This optimal power has been estimated for eleven 16-bit multiplier architectures.KeywordsClock CycleTotal Power ConsumptionLogical DepthLeakage ReductionDynamic Power DissipationThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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