Leakage power-aware clock skew scheduling

Abstract

Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is stolen from fast combinational blocks to be used by slower blocks to meet a more stringent clock cycle time. Instead, we can leverage on the borrowed time to achieve leakage power reduction during gate sizing and/or dual Vth assignment. In this paper, we present the first approach to the best of our knowledge for integrating clock skew scheduling, threshold voltage assignment, and gate sizing into one optimization formulation. Over 29 circuits in the ISCAS89 benchmark suite, this integrated approach can reduce leakage power by as much as 55.83% and by 18.79% on average, compared to using combinational circuit based power optimization on each combinational block without considering clock skews. Using a 65 nm dual Vth technology library, this corresponds to a 23.87% peak reduction (6.15% on average) in total power at the ambient operating temperature. The average total power reduction further increases to 9.83% if the high temperature library of the same process technology is used.