Leakage Power Reduction in Deep Submicron VLSI Circuits Using Delay-Based Power Gating

Abstract

Among various available techniques, power gating is a well-known method which is widely employed to minimize the leakage power in CMOS design. This paper proposes a delay-based power gating technique to minimize the leakage power in adders and multipliers. The proposed technique is verified using both fine-grain and coarse-grain power gating methodology. To validate the efficiency of the proposed method, the experimental analysis has been carried out in terms of leakage power and area. The results obtained from the experimental analysis indicate that the proposed method achieves 14.33% improvement in fine-grained power gating and 5.47% improvement in coarse-grained power gating in terms of average leakage power dissipation when compared with conventional power gating technique.