Leakage power reduction for domino circuits in 45nm CMOS technologies

Abstract

A new circuit technique is proposed in this paper for reducing both the subthreshold and gate oxide leakage power in the domino logic circuits. Three high-V t sleep transistors are added to the standard domino logic circuit to place the circuit into low leakage state. Proposed circuit is evaluated at 110°C and 25°C. At 110°C, proposed circuit reduces leakage power consumption by up to 63%, and at 25°C, it reduces by up to 95.3% as compared to standard dual-V t domino circuits. Similarly, our proposed circuit reduces leakage power consumption at 110°C by 83.5%, and at 25°C, it reduces up to 95.7% as compared to standard low-V t domino circuits.