Leakage mitigation for low power microcontroller design in 40nm for Internet-of-Things (IoT)

Abstract

Modern systems for ubiquitous computing domains such as Internet-of-things (IoT), wearable computing etc. are characterized by low duty cycle, low operating and stand by power consumption requirements. The design of such systems is further constrained by increasing leakages due to technology scaling and/or increased data retention requirements. These conflicting requirements make leakage reduction of digital logic and SRAM a primary objective for efficient system realization. In this work, we discuss the effectiveness of advance leakage reduction techniques in 40nm (HYT technology) for SRAM and digital logic. For SRAM memory, adding error correction coding (ECC) to the memory subsystem can provide new trade-offs which will be advantageous for these low-duty cycle systems. We show that decreasing the data retention voltage while preventing errors using ECC will help decrease the leakage current by 45% (leakage power by 70% for SRAM). For the digital logic, test and simulation data shows that reverse body biasing (RBB) can reduce the logic leakage current by ∼3x in the worst case process and temperature conditions. However, it should be carefully implemented as RBB causes increase in leakage current at nominal temperatures due to higher junction currents. Moreover, the asymmetric biasing where PMOS is biased by 0.7V and NMOS by 0.3V provides optimum results. RBB can also help reducing the switching energy at low frequency due to increased contribution of leakage to total energy compare to conventional technologies. We also show that increasing the gate length by 20% can help reduce the leakage current by 2x while there is minimal penalty on dynamic power and speed. Combining the asymmetric RBB application and increased gate-length can result in ∼6x leakage reduction.