Leakage current reduction due to hot carrier effects in n-channel polycrystalline silicon thin film transistors

Abstract

As is well known, the application of gate-voltage stresses in conjunction with high source-drain voltages, V ds, modifies the electrical characteristics of polycrystalline silicon thin film transistors. In particular negative gate-voltage stresses on n-channel devices usually reduce both the leakage current and the transconductance. In this paper a complete analysis of hot carrier effects induced by different gate-bias stresses at high V ds is presented and discussed in terms of trap and interface state creation. It is shown that in certain stress regimes the leakage current can be reduced without the accompanying transconductance degradation.