Abstract

Leakage currents as low as 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-7</sup> A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at both 1 V and -1 V top electrode bias in the sub-0.4-nm equivalent SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> thickness range are demonstrated in Ru/SrTiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /Ru metal- insulator-metal capacitors in which the 8.5-nm SrTiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> layer is deposited by atomic layer deposition. The top electrode material and deposition technique as well as the postdeposition anneal are crucial parameters to control the leakage, not only at negative, but also at positive top electrode bias.

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