Leakage control for deep-submicron circuits

Abstract

High leakage current in deep sub-micron regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, leakage control and reduction are very important, especially for low power applications. The reduction in leakage current has to be achieved using both process and circuit level techniques. At the process level, leakage reduction can be achieved by controlling the dimensions (length, oxide thickness, junction depth, etc) and doping profile in transistors. At the circuit level, threshold voltage and leakage current of transistors can be effectively controlled by controlling the voltages of different device terminals (drain, source, gate, and body (substrate)).