Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era

Abstract

Low-voltage scaling limitations of memory-rich CMOS LSIs are one of the major problems in the nanoscale era because they cause the evermore-serious power crisis with device scaling. The problems stem from two unscalable device parameters: The first is the lowest necessary threshold voltage, Vt (Vt0), required for MOSFETs to keep the subthreshold current (leakage) low; unfortunately, this voltage usually has a high and constant value (e.g., 0.2--0.4 V). The second is the variation in Vt (ΔVt), that becomes more prominent in the nanoscale era. The ΔVt caused by the intrinsic random dopant fluctuation is the major source of various ΔVt components. It increases with device scaling and thus enhances various detrimental effects including variations in speed and/or the voltage margin of circuits, and it significantly increases soft-error rates in RAM cells and logic gates. For example, the speed variation (ΔA) of a MOSFET—that is, the ratio of the slowest speed at the highest Vt to the average speed at the average Vt (HVt0) —is approximately given as {1--Vtmax/(VDD --Vt0)}-1.2, where ΔVtmax is the maximum variation in Vt in a circuit, block, or chip, and VDD is the actual operating voltage. Fortunately, for conventional MOSFETs, the ΔA was negligible up to about the 100-nm device generation because of a VDD much higher than the Vt0 and a small enough ΔVtmax. In the nanoscale era below the 100-nm generation, however, the ΔA rapidly increases due to the ever-larger ΔVtmax with device scaling. If the VDD is reduced, the increase is accelerated as the VDD is reduced across 1 V and approaches Vt0. In practice, the VDD cannot be reduced at all since the increase in the ΔA must be confined to a tolerable value for reliable operation. It is the minimum operating voltage (Vmin), which is defined as the VDD necessary for the tolerable ΔA. Vmin is thus expressed as Vmin = Vt0 + (1+γ)ΔVtmax. Here, γ depends on ΔA and is 2.1 for ΔA = 1.6 and 3.1 for ΔA = 1.4. Due to an increased Vmin caused by such inherent features of the Vt0 and ΔVt, the VDD, which must be higher than Vmin, is facing the 1-V wall in the 65-nm generation and is expected to rapidly increase with further device scaling, thereby worsening the power crisis. For the LSI industry to continue to proliferate, the 1-V wall must be breached, and the door to the 0.5-V nanoscale era must be opened by reducing the Vmin. In addition to more stringent control of intra-die and inter-die Vt variations, developments of circuits and devices to reduce the Vt0 and ΔVtmax are extremely crucial.Reviews of and perspectives on low-voltage circuits for nanoscale memory-rich CMOS LSIs are described in this talk, focusing mainly on the leakage and variability issues of MOSFETs. First, state-of-the-art low-voltage circuits are reviewed in terms of reducing the Vmin. The Vmins of logic, SRAM, and DRAM blocks are compared, revealing that the SRAM block is the most problematic because it has the highest Vmin. SRAM cells, exemplified by 6- and 8-transistor cells, are then reviewed with respect to the Vmin and cell size. Next, perspectives on the 0.5-V nanoscale CMOS era are described, including proposals of some breakthrough technologies. Here, advanced MOSFETs (e.g., high-k metal-gate MOSFETs and FinFETs) for reducing Vmins is discussed, followed by dual-VDD/dual-Vt dynamic circuits for further reducing Vmins. A differentially driven power switch suitable for multi-core LSIs and a tiny logic-process-compatible FinFET DRAM cell for reducing the core or chip size, which has been dominated by the SRAM array, are described as well. They maintain the reduced Vmin through reducing power supply noise. Finally, a scenario for 0.5-V nanoscale CMOS LSIs is presented.