LDPC Level Prediction Toward Read Performance of High-Density Flash Memories

Abstract

High-density NAND flash memories have been prevailing in storage systems to achieve large capacities for explosive data. However, they suffer from more severe reliability degradation due to the narrowed margins between threshold voltage states. LDPC codes have been widely applied in high-density flash memories to ensure data reliability. Due to the increased number of cell states, more read voltages are required in reading a flash page correctly. This induces more soft levels to read pages with high bit error rates in LDPC decoding. Read latency is significantly increased in high-density flash memories. To enhance the read performance of high-density flash memories, this paper proposes PreLDPC, an LDPC level prediction approach with fine-grained LDPC reading. The key idea of PreLDPC is to predict the final read level during the early read iteration, thus avoiding unnecessary read-retry latency. From a preliminary study, we observe that after decoding in the first two iterations, the ratio of cells that lie in error-prone area (i.e. adjacent area of two cell states) can be obtained. The ratio is closely related to the final read level for a successful decoding. By exploiting this observation, PreLDPC directly uses the predicted read level for LDPC reading, which could eliminate excessive number of read retries. Furthermore, by exploiting the benefit of fine-grained LDPC reading, this paper further divides the existing integer level (called i-level, e.g. level-1 and level-2) into finer decimal level (called d-level, e.g. level-1.25 and level-1.5), and proposes a fine-grained read method. By combining the prediction method and fine-grained method together, PreLDPC can first estimate the i-level and then perform the read-retry iteration with d-levels to eliminate unnecessary read latency as much as possible. From experimental results of real-world workloads on Disksim with SSD extensions, it is verified that PreLDPC can effectively reduce read latency in high-density flash memories.