LDPC Decoder of High Speed Multi-Rate DVB-S2 Based on FPGA

Tianjiao Xie,Bo Li,Mao Yang,Zhongjiang Yan

doi:10.1051/jnwpu/20193720299

Abstract

A multi-rate LDPC decoder architecture for DVB-S2 codes based on FPGA is proposed. Through elementary transformation on the parity check matrices of DVB-S2 LDPC codes, a new matrix whose left is a QC sub-matrix and right is Transformation of Staircase lower triangular (TST) sub-matrix is obtained. The QC and TST are designed separately, therefore the successful experience of the most popular Quasi-Cyclic (QC) LDPC decoder architecture can be drawn on. While for TST sub-matrix, the variable nodes updating only need to be considered and the check nodes updating is realized compatibility with QC sub-matrix. Based on the proposed architectures, a multi-rate LDPC decoder implemented on Xilinx XC7VX485T FPGA can achieve the maximum decoding throughput of 2.5 Gbit/s at the 20 iterations when the operating frequency is 250 MHz, which demonstrates the highest throughput compared with the state-of-the-art works.

Highlights

A multi⁃rate LDPC decoder architecture for DVB⁃S2 codes based on FPGA is proposed
Based on the proposed architectures, a multi⁃ rate LDPC decoder implemented on Xilinx XC7VX485T FPGA can achieve the maximum decoding throughput of 2.5 Gbit / s at the 20 iterations when the operating frequency is 250 MHz, which demonstrates the highest throughput compared with the state⁃of⁃the⁃art works
Æ1.School of Electronics and Information, Northwestern Polytechnical University, Xi′an 710072, China;ö ç

Summary

Ht 的 dc

见 1.2 节,处理单元 CNU 和 VNU 占用了译码器的大部分资源,为了有效地对码率兼容 LDPC 码译码器进行设计,不同码率之间应该最大程度地共享处理单元资源。通过对表 2 进行分析,可以得到 2 种处理单元 CNU 和 VNU 的最小数量。校验节点单元 CNU 用来进行行信息的更新,将行重设计为 13 可以兼容 10,11,12,13 行重情况,所以码率兼容译码器需要 3 种行重情况 { 6 ( 27 ) , 13 ( 18 ) , 27 (5) } ,译码器需要 27p 个 6 输入的 CNU,18p 个 13 输入和 5p 个 27 输入的 CNU, 分别记为 CNU6, CNU13 和 CNU27,这里 p 表示块内的并行度数。同理,变量节点更新单元 VNU 用来进行列信息的更. 需要存储,本文采用存储块 RAM - M 和 MCt 分别来存储 QC 准循环矩阵 H1t 和 TST 矩阵 H2t 所对应的外信息。 H2t 的非零元素采用数组 E[ c] [ d] 来表示, 其中,列标为 c(1 ≤ c ≤ q × L) ,因为 H2t 的行重为 1 或 2,令 d(0 ≤ d ≤ 1) 表示 H2t 的第 d 个非零元素。从图 2 中可见 H2t 共有 2q 个非零元素,分别为:. 器 MCt,x 的内容可知,与其对应的列号分别为 0 + y, q + y,2q + y,...,q × ( L - 1) + y,y(0 ≤ y ≤ q - 1) , 所以 VNU 处理单元工作阶段,Ft 需要与 2 个存储器 MCt,x 进行数据交互。 2.4 提出的 DVB⁃S2 标准的码率兼容 LDPC 码译. 器架构需要 3 种存储器资源: 信道信息存储器 ( RAM- QC, RAM- TST) 、外信息存储器 ( RAM- M, RAM- C) 和硬判决存储器,每个存储器采用的深度均为 2「L / p⌉,为了保证译码器在接收信道信息的同

RAMMC MCt

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