Abstract
A simple and nonlinear LDMOS transistor model with multi-bias consideration has been proposed. Elements of the model are optimizes using particle swarm optimization (PSO) algorithm to flt the measured RF speciflcations of a typical transistor. The developed model is used then to design a high e-ciency power amplifler with 55% power added e-ciency (PAE) at 33dBm output power with 12dB power gain. This amplifler has a novel topology with optimized BALUN and microstrip matching network which makes it unconditionally stable and extensively linear over UHF frequency range of 100MHz to 1GHz with 163% fractional bandwidth. This power amplifler is fabricated and realized with 12-V supply voltage. A good agreement between simulated and measured values observed, indicating high accuracy of either the model and the amplifler design approach.
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