LDD implant process optimization for high voltage NMOS improvement

Abstract

In this paper, we demonstrate that high voltage NMOS is very sensitive to LDD implant process conditions. With the same implant energy and dose, high voltage NMOS channel punch through BVDSS tail is strongly toggled by critical implant process parameters such as beam current and beam size. Lower beam current density reduces both implant damage and beam angular divergence. As a result, LDD lateral junction tail under the channel is shortened and the variation of the channel punch-through is reduced. However, lower beam current degrades the throughput and increases the cost of the implant. On the other hand, longer effective channel length reduces HV NMOS sensitivity to LDD implant beam current and enables higher beam current implant without BVDSS tail, but there is trade-off on other device performance and it is limited by design rules. From device point of view, lower beam current implant is often chosen as the final solution with the price for higher implant cost. This study is very important for us to understand that when we optimize the implant process setup, we should not only consider about throughput improvement by pushing up higher beam current, but also closely watch device sensitivity to different implant process setup.